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16- bit lower power pulsar adcs in msop/ lfcsp ( qfn ) data sheet ad7988 - 1 / ad7988 - 5 rev. b info rmation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specificat ions subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features low power dissipation ad7988 - 5 : 3.5 mw @ 500 ksps ad7988 - 1 : 700 w @ 100 ksps 16- bit resolution with no missing codes throughput: 1 00 k sps /500 ksps opt ions inl: 0.6 lsb typ ical , 1.25 lsb max imum si n a d: 91 .5 db @ 1 0 khz thd: ? 1 1 4 db @ 1 0 khz pseudo differential analog input range 0 v to v ref with v ref from 2.5 v to 5.5 v any input range and easy to drive with the ada4841 - 1 no pipeline delay single - supply 2.5 v operation with 1.8 v /2.5 v/3 v/5 v logic interface spi - /qspi - /microwire? - /dsp - compatible s erial interface daisy - chain multiple adcs 10- lead msop and 10 - lead, 3 mm 3 mm lfcsp ( qfn ), same space as sot - 23 wide operating temperature range: ? 40c to +125c applications batter y - powered equipment low power d ata a cquisition systems portable m edical instruments ate equipment data acquisitions communications general description the ad7988 - 1 / ad7988 - 5 are 16 - bit, successive approximation, analog - to - digital converter s (adc) that operate from a single power supply, vdd. the ad7988 - 1 offers a 1 00 ksps throughput , and the ad7988 - 5 offers a 500 ksps throughput. they are low power, 16- bit sampling adc s with a versatile serial interface port. on the cnv rising edge, they sample an analog input , in+ , between 0 v to v ref with respect to a ground sense , in ? . the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. the spi - compatible serial interface also features the ability to daisy - chain several a dcs on a single 3 - wire bus using the sdi input . it is compati ble with 1.8 v, 2.5 v, 3 v, or 5 v logic using the separate supply , vio. the ad7988 - 1 / ad7988 - 5 generic s are housed in a 10 - lead msop or a 10 - lead lfcsp ( qfn ) wi th operation specified from ? 40c to + 12 5c. table 1 . msop, lfcsp ( qfn ) 14 - /16- /18- bit pulsar ? adc s bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 1 8 1 ad7691 2 ad7690 2 ad7982 2 ad7984 2 ada4941 - 1 ada4841 - 1 16 1 ad7684 ad7687 2 ad7688 2 ad7693 2 ada4941 - 1 ada4841 - 1 16 3 ad7680 ad7683 ad7988 - 1 2 ad7685 2 ad7694 ad7686 2 ad7988 - 5 2 ad7980 2 ada4841 - 1 ada4841 - 1 ada4841 - 1 14 3 ad7940 ad7942 2 ad7946 2 ada4841 - 1 1 true differential. 2 pin - for - pin compatible. 3 pseudo differential. typical application diagram ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v t o 5.5v 3- or 4-wire inter f ace (spi, dais y chain, cs) 2.5v t o 5v 2.5v 0v t o v ref 10231-001 ad 7 9 88 - 1 / ad 7 9 88 - 5 figure 1 .
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application diagram .......................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 typical connection diagram ................................................... 15 analog inputs ............................................................................. 16 driver amplifier choice ........................................................... 16 voltage reference input ............................................................ 17 power supply ............................................................................... 17 digital interface .......................................................................... 17 cs mode, 3 - wire ........................................................................ 18 cs mode 4 - wire ......................................................................... 19 chain mode ................................................................................ 20 applications information .............................................................. 21 interfacing to blackfin? dsp ..................................................... 21 layout .......................................................................................... 21 evaluating the performance of the ad7988 - x ........................ 21 outline dimensions ....................................................................... 22 o rdering guide .......................................................................... 23 revision history 5/12 rev. a to rev. b ch anges to table 3 ............................................................................. 4 updated outline dimensions ........................................................ 22 2/ 12 rev. 0 to rev. a added lfcsp thermal impedance values ................................... 7 updated outline dimensions ....................................................... 23 changes to ordering gui de .......................................................... 23 2 /12 revision 0 : initial versi on
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 3 of 24 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C 40c to + 12 5c, unless otherwise noted. table 2. parameter test conditions /comments min typ max unit resolution 16 bits analog input voltage range in+ ? in? 0 v ref v absolute input voltage in+ ? 0.1 v ref + 0.1 v in? ? 0.1 +0.1 v analog input cmrr f in = 1 khz 60 db leakage current at 25c acquisition phase 1 na input impedance see the analog inputs section accuracy no missing codes 16 bits differential linearity error v ref = 5 v ? 0.9 0.4 +0.9 lsb 1 v ref = 2.5 v 0.55 lsb 1 integral linearity error v ref = 5 v ? 1.25 0.6 +1.25 lsb 1 v ref = 2.5 v 0.65 lsb 1 transition noise v ref = 5 v 0.6 lsb 1 v ref = 2.5 v 1.0 lsb 1 gain error, t min to t max 2 2 lsb 1 gain error temperature drift 0.35 ppm/c zero error, t min to t max 2 ? 0.5 0.08 +0.5 mv zero temperature drift 0.54 ppm/c power supply sensitivity vdd = 2.5 v 5% 0.1 lsb 1 throughput ad7988 - 1 conversion rate vio 2.3 v up t o 85c, vio 3.3 v above 85c up to 125c 0 100 ksps transient response full - scale step 500 ns ad7988 - 5 conversion rate vio 2.3 v up to 85c, vio 3.3 v above 85c up to 125c 0 500 ksps tran sient response full - scale step 400 ns ac accuracy dynamic range v ref = 5 v 92 db 3 v ref = 2.5 v 87 db 3 oversampled dynamic range f o = 10 ksps 111 db 3 signal -to - noise ratio , snr f in = 10 khz, v ref = 5 v 90 91 db 3 f in = 10 khz, v ref = 2.5 v 86.5 db 3 spurious - free dynamic range, sfdr f in = 10 khz ? 110 db 3 total harmonic distortion, thd f in = 10 khz ? 114 db 3 signal - to - (noise + distortion), sinad f in = 10 khz, v ref = 5 v 91.5 db 3 f in = 10 khz, v ref = 2.5 v 87.0 db 3 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 76.3 v. 2 see the terminology section. these specifications include full temperature range variation , but not the error contribution from the external reference. 3 all specifications in db are referred to a full - scale input fs r . tested with an input signal at 0.5 db below full scale, unless otherwise specified.
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 4 of 24 vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C 40c to + 12 5c, unless otherwise noted. table 3. parameter test conditions /comments min typ max unit reference voltage range 2.4 5.1 v load current v ref = 5 v 250 a sampling dynamics ? 3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2.0 ns digital inputs logic levels v il vio > 3 v C0.3 0.3 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v v il vio 3 v C0.3 0.1 vio v v ih vio 3 v 0.9 vio vio + 0.3 v i il ? 1 +1 a i ih ? 1 +1 a digital outputs data format serial 16 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power s upplies vdd 2.375 2.5 2.625 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v, 25c 0.35 na ad7988 - 1 power dissipation 10 ksps throughput 70 w 100 ksps throughput 700 w 1 mw ad7988 - 5 power dissipation 500 ksps throughput 3.5 5 m w energy per conversion 7.0 nj/sample temperature range specified performance t min to t max ? 40 +125 c 1 with all digital inputs forced to vio or gnd as required. 2 during the acquisition phase.
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 5 of 24 timing specification s vdd = 2.37 v to 2.63 v, vio = 3 .3 v to 5.5 v, ?40c to +125c unless otherwise stated. see figure 2 and figure 3 for load conditions. table 4. parameter symbol min typ max unit ad7988 - 1 throughput rate 100 khz conversion time: cnv rising edge to data available t conv 9.5 s acquisition time t acq 500 n s time between conversions t cyc 10 s ad7988 - 5 throughput rate 500 khz conversion time: cnv rising edge to data available t conv 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse width ( cs mode) t cnvh 500 ns sck period ( cs mode) t sck vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4 .5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3v 15 ns cnv or sdi high or last sck falling e dge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sdi valid hold time from cnv risi ng edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sd i valid hold time from sck falling edge (chain mode) t hsdisck 3 ns
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 6 of 24 500 a i ol 500 a i oh 1.4v t o sdo c l 20pf 10231-002 figure 2 . load circuit for digital interface timing x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 10231-003 figure 3 . voltage levels for timing
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 7 of 24 absolute maximum rat ings table 5. parameter rating analog inputs in+ , 1 in? 1 to gnd ? 0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ? 0.3 v to + 6 v vdd to gnd ? 0.3 v to +3 v vdd to vio + 3 v to ? 6 v digital inputs to gnd ? 0.3 v to vio + 0.3 v digital outputs to gnd ? 0.3 v to vio + 0.3 v storage temperature range ? 65c to +1 25c junction temperature 150c ja thermal impedance 10- lead msop 200c/w 10- lead lfcsp 8 0c/w jc thermal impedance 10- lead msop 44c/w 10- lead lfcsp 15 c/w reflow soldering jedec standard (j - std -020) 1 see the analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 8 of 24 pin configuration s and funct ion descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 10231-004 a d 79 8 8-1 / a d 79 8 8- 5 t o p v i ew ( n o t t o sc a l e ) figure 4 . 10 - lead msop pin configuration notes 1. the exposed p ad can be connected t o gnd. 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv 10231-005 a d 7 9 88-1 / a d 7 9 88- 5 t o p v i e w ( n o t t o s ca l e ) figure 5 . 10 - lead lfcsp ( qfn ) pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 descri ption 1 ref ai reference input voltage. the v ref range is from 2. 4 v to 5. 1 v. it is referred to the gnd pin. the gnd pin should be decoupled closely to the ref pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai analog input. it is referred to in?. the voltage range, for example , the difference between in+ and in?, is 0 v to v ref . 4 in? ai analog input ground sense. connect to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part : chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, t he data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows : chain mode is selected if this pin is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the co nversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low . 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). ep exposed pad. the exposed pad can be connected to gnd. 1 ai = analog input, di = digital input, do = digital output, and p = p ower .
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 9 of 24 terminology int egral nonlinearity error (inl) i nl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full sc ale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line ( see figure 30). differential nonlinearity error (dnl) in an ideal adc, code transit ions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v f or the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111 10 to 111 11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of th e input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula : enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code re solution noise - free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise - free code r esolution = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective r esolut ion effective resolution is calculated as effective r esolution = log 2 (2 n / rms input no ise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in db. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in db. it is measured with a signal at ? 6 0 dbf s to include all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the val ue for snr is expressed in db. signal -to - (noise + distortion) ratio (s i n a d) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. th e value for sinad is expressed in db. aperture delay aperture delay is t he measure of the acquisition performance . i t is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response t ransient resp onse is t he time required for the adc to accurately acquire its input after a full - scale step function i s applied .
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 10 of 24 typical performance characteristics vdd = 2.5 v, v ref = 5.0 v, vio = 3.3 v , unless otherwise noted. 0 ?180 f r eq u en c y ( kh z) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 f s = 500ksps f in = 10khz snr = 91.17db thd = ?113.63db sfdr = 110.30db sinad = 91.15db amplitude (db of full scale) 0 50 100 150 200 250 10231-046 figure 6 . ad7988 - 5 fft plot, v ref = 5 v 0 ?180 f r eq u en c y ( kh z) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 f s = 500ksps f in = 10khz snr = 86.8db thd = ?111.4db sfdr = 105.9db sinad = 86.8db amplitude (db of full scale) 0 50 100 150 200 250 10231-047 figure 7 . ad7988 - 5 fft plot, v ref = 2.5 v 0 ?180 f r eq u en c y ( kh z) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 f s = 100ksps f in = 10khz snr = 91.09db thd = ?113.12db sfdr = 110.30db sinad = 91.05db amplitude (db of full scale) 0 10 20 30 40 50 10231-048 f igure 8 . ad7988 - 1 fft plot, v ref = 5 v 0 ?180 f r eq u en c y ( kh z) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 f s = 100ksps f in = 10khz snr = 86.7db thd = ?110.4db sfdr = 103.9db sinad = 86.6db amplitude (db of full scale) 0 10 20 30 40 50 10231-049 figure 9 . ad7988 - 1 fft plot, v ref = 2.5 v 1. 2 5 ? 1. 2 5 code in l ( l s b) 1.0 0 0.7 5 0.5 0 0.2 5 ? 0. 25 ? 0. 75 0 ? 0. 50 ? 1. 00 po s i t i v e i n l : +0 . 4 0 l s b ne g a t i v e in l : ?0 . 35 ls b 0 16384 32768 49152 65536 10231-010 figure 10 . integral nonlinearity vs. code , v ref = 5 v 1. 2 5 1. 0 0 ? 1 . 2 5 ? 1 . 0 0 in l ( l s b ) 0.7 5 0.5 0 0.2 5 ? 0 . 2 5 ? 0 . 7 5 0 ? 0 . 5 0 po s i t i v e i n l : +0 . 4 5 l s b ne g at i v e in l : ?0 . 2 9 ls b code 0 16384 32768 49152 65536 10231-011 figure 11 . integral nonlinearity vs. code, v ref = 2.5 v
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 11 of 24 code 0 16384 32768 49152 65536 1 . 0 0 ?1 . 0 0 d n l ( l s b ) 0 . 7 5 0 . 5 0 0 . 2 5 ? 0 . 2 5 ? 0 . 7 5 0 ? 0 . 5 0 p o s i t i ve i n l : + 0 . 1 8 l s b n e g a ti ve i n l : ? 0 . 2 1 l s b 10231-012 figure 12 . differential nonlinearity vs. code, v ref = 5 v code 0 16384 32768 49152 65536 1 . 0 0 ?1 . 0 0 d n l ( l s b ) 0 . 7 5 0 . 5 0 0 . 2 5 ? 0 . 2 5 ? 0 . 7 5 0 ? 0 . 5 0 p o s i t i ve i n l : + 0 . 2 5 l s b n e g a ti ve i n l : ? 0 . 2 2 l s b 10231-013 figure 13 . differential nonlinearity vs. code, v re f = 2.5 v 180k 0 0 0 0 0 0 22 code in hex cou n t s 8003 8004 8005 8006 8007 8008 8009 800a 800b 800c 800d 800e 800f 1291 852 29 2 10231-050 160k 140k 120k 100k 80k 60k 40k 20k 52720 162595 42731 figure 14 . histogram of a dc input at the code center , v ref = 5 v 6 0 k 0 0 0 0 0 9 4 30 1 code in hex cou n t s 5 0 k 3 0 k 1 0 k 4 0 k 2 0 k 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 2 29 0 18 8 4 8 5 0 97 0 4 5 19 8 1 2 42 4 1 21 7 10231-015 figure 15 . histogram of a dc input at the code transition, v ref = 2. 5 v 10 0 8 0 8 5 9 0 9 5 r e f e r e nc e v o l t a g e ( v ) s nr , s i na d ( d b ) 1 6 1 2 1 3 1 4 1 5 e n o b ( b i t s ) s n r s i na d e n o b 2.25 2.75 3.25 3.75 4.25 4.75 5.25 10231-016 figure 16 . snr, sina d, and enob vs. reference voltage 6 0 k 0 0 0 0 0 590 11 19 code in hex cou n t s 5 0 k 3 0 k 1 0 k 4 0 k 2 0 k 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 7285 37417 53412 31540 5807 512 10231-051 figure 17 . histogram of a dc input at the code center, v ref = 2.5 v
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 12 of 24 9 5 8 5 8 7 8 9 9 2 9 1 9 3 9 4 8 6 8 8 9 0 i n p u t l e ve l (d b o f f u l l s c a l e ) s nr ( d b ) ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 10231-018 figure 18 . snr vs. input level ?9 5 ?12 5 ? 1 1 0 ? 1 1 5 ?10 5 ?10 0 ?12 0 1 1 5 8 5 1 0 0 9 5 1 0 5 1 1 0 9 0 r e f e r e nc e v o l t a g e ( v ) t hd ( d b ) s f dr ( d b ) t h d s f d r 2.25 2.75 3.25 3.75 4.25 4.75 5.25 10231-019 figure 19 . thd, sfdr vs. reference voltage 100 80 10 1k frequency (khz) sinad (db) 95 90 85 100 10231-052 figure 20 . sinad vs. frequency 10231-053 95 85 89 87 91 93 ?55 125 temperature (c) snr (db) ?35 ?15 5 25 65 85 45 105 figure 21 . snr vs. temperature 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 . 1 0 vd d volt a g e ( v) i vdd i ref i vio current (ma) 2.375 2.425 2.475 2.525 2.575 2.625 10231-023 figure 22 . operating currents vs. supply ( ad7988 - 5 ) 0 .1 4 0 .1 2 0 .1 0 0 .0 8 0 .0 6 0 .0 4 0 .0 2 0 vd d volt a g e ( v) i vdd i ref i vio current (ma) 2.375 2.425 2.475 2.525 2.575 2.625 10231-024 figure 23 . operating currents vs. supply ( ad7988 - 1 )
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 13 of 24 10231-054 ?85 ?125 10 1k frequency (khz) thd (db) 100 ?90 ?95 ?100 ?105 ?110 ?115 ?120 figure 24 . thd vs. frequency ?1 1 0 ? 12 0 t hd ( d b ) t e m p e r a t ur e ( c ) ?11 2 ?11 4 ?11 6 ?11 8 ?55 ?35 ?15 5 25 45 65 85 105 125 10231-026 figure 25 . thd vs. temperature 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 current (ma) i vdd i ref i vio t e m p e r a t ur e ( c ) ?55 ?35 ?15 5 25 45 65 85 105 125 10231-027 fi gure 26 . operating currents vs. temperature ( ad7988 - 5 ) 0 .1 4 0 .1 2 0 .1 0 0 0 8 0 .0 6 0 .0 4 0 . 0 2 0 current (ma) i vdd i ref i vio t e m p e r a t ur e ( c ) ?55 ?35 ?15 5 25 45 65 85 105 125 10231-028 figure 27 . operating currents vs. temperature ( ad798 8 - 1 ) 8 7 6 5 4 3 2 1 0 current (a) temperature (c) i vdd + i vio ?55 ?35 ?15 5 25 45 65 85 105 125 10231-029 figure 28 . power - down currents vs. temperature
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 14 of 24 theory of operation comp switches control busy output code cnv control logic sw+ lsb sw? lsb in+ ref gnd in? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c 10231-030 figure 29 . adc simplified schematic circuit information the ad7 988- 1 / ad7988 - 5 device s are fast, low power, single - supply, precise 16 - bit adc s that us e a successive approximation architecture. the ad7988 - 1 is capable of co nverting 100,000 samples per second (1 00 ksps) , whereas the ad7988 - 5 is capable of a throughput of 500 ksps , and they power down between conversions. when operating at 10 ksps, for example, the adc consumes 7 0 w typically, ideal for battery - powered applications. the ad7988 - x provides the user with on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7988 - x can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10 - lead msop or a tiny 10 - lead lfcsp ( qfn ) that combines space savings and allows flexible config urations. converter operation the ad7988 - x is a successive approximation adc based on a charge redistribution dac. figure 29 shows the simplified schematic of the adc. the capacitive da c consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independen t switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete d and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase are applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /65 , 536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase and the control logic gen erates the adc output code . because the ad7988 - x has an on - board conversion clock, the serial clock, sck, is not required for the conversion process.
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 15 of 24 transfer functions the ideal transfer characteristic for the ad7988 - x is shown in figure 30 and table 7 . 000 ... 000 000 ... 001 000 ... 010 11 1 ... 101 11 1 ... 1 10 11 1 ... 11 1 ?fsr ?fsr + 1lsb ?fsr + 0.5lsb +fsr ? 1 lsb +fsr ? 1.5 lsb analog input adc code (straight binary) 10231-031 figure 30 . adc ideal transfer function table 7 . output codes and idea l input voltages analog input description v ref 5 v digital output code ( he ) fsr C 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff C fsr + 1 lsb 76.3 v 0001 C fsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection d iagram figure 31 shows an example of the recommended connection diagram for the ad7988 - x when multiple supplies are available. ad7988-1/ ad7988-5 2.5v v+ 20 v+ v? 0v to v ref 1.8v to 5.5v 100nf 10f 2 2.7nf 4 3 100nf ref in+ in? vdd vio gnd 3- or 4-wire interface 5 ref 1 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see the driver amplifier choice section. 4 optional filter. see the analog inputs section. 5 see the digital interface section for the most convenient interface mode. 10231-032 cnv sck sdo sdi figure 31 . typical application diagram with multiple supplies
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 16 of 24 analog input s figure 32 shows an equivalent circuit of the inp ut structure of the ad7988 - x . the two diodes, d1 and d2, provide esd protection for the analog inputs , in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v , because this causes these diodes to be come forward - bias ed and start conducting current. these diodes can handle a forward - biased curr ent of 130 ma maximum. for instance, these conditions may eventually occur when the input buffers supplies are different from vdd. in such a case (for example, an input buffer with a short circuit ) , the current limitation can be used to protect the part. ref r in c in in+ or in? gnd d2 c pin d1 10231-033 figure 32 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ and i n?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component made up of serial resistors and the on re sistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . r in and c in make a one - pole, low - pass filter that reduces undesira ble aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7988 - x can be driven directly. large source impedances significantly affect the ac performance, especial ly thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifie r choice although the ad7988 - x is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr an d transition noise performance of the ad7988 - x . the noise coming from the driver is filtered by the ad7988 - x analog in put circuit s one - pole, low - pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7988 - x is 47.3 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3db 2 ) ( 2 47.3 47.3 log 20 n loss ne f snr where: f C 3db is the input bandwidth in mhz of the ad7988 - x (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buff er configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ad7988 - x . ? for multichannel multiplexed applications, the driver ampli - fier and the ad7988 - x analog input circuit must settle for a full - scale step onto the capacitor array at a 16 - bit level (0.0015%, 15 ppm). in the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly fr om the settling time at a 16 - bit level and should be verified prior to driver selection. table 8 . recommended driver amplifiers amplifier typical application ada4841 -1 very low noise, small size , and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, l ow noise, and low frequency ad8655 5 v single - supply, low noise ad8605 , ad8615 5 v single - supply, low power
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 17 of 24 voltage re ference input the ad7988 - x voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explain ed in the layout s ection. whe n ref is driven by a very low impedance source, for example , a reference buffer using the ad8031 or the ad8605 , a ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for example , a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performa nce using a low temperature drift adr43x reference. if desired, a reference - decoupling capacitor value as small as 2.2 f can be used with a minimal impact on performance, especially dnl. r egardless, there is n o need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7988 - x uses two power supply pins: a core supply, vdd, and a digital inpu t/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and 5.0 v. to reduce the number of supplies needed, vio and vdd can be tied together. the ad7988 - x is independent of powe r supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 33. 80 55 1 1k frequency (khz) psrr (db) 10 100 75 70 65 60 10231-034 figure 33 . psrr vs. frequency to ensure optim um performance, vdd should be roughly half of ref, the voltage reference input. for example, if ref is 5.0 v, vdd should be set to 2.5 v (5%). if ref = 2.5v, and vdd = 2.5 v, performance is degraded as can be seen in table 2 . the ad7988 - x powers down automatically at the end of each conversion phase . digital interface alt hough the ad7988 - x has a reduced number of pins, it offers flexibilit y in its serial interface modes. the ad7988 - x , when in cs mode, is compatible with spi, qspi ? , and digital hosts. this interface can use either a 3 - wire or 4 - wire interface . a 3 - wire inte rface using the cnv, sck, and sdo signals minimizes wiring connections and is useful, for instance, in isolated applications. a 4 - wire interface using the sdi , cnv, sck, and sdo signals allows cnv, which initiates the conver sions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7988 - x , when in chain mode, provides a daisy - chain feature using the sdi input for cascading multiple a dcs on a single data line , similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high , and chain mode is selected if sdi is low. the s di hold time is such that when sdi and cnv are connected together, the chain mode is selected. t he user must time out the maximum conversion time prior to readback.
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 18 of 24 cs m ode , 3 - wire this mode is typically used when a single ad7988 - x is connected to an spi - compatible digital host. the connection diagram is shown in figure 34 , and the corresponding timing is given in figure 35. with sdi tie d to vio, a rising edge on cnv initiates a conver - sion, selects the cs mode, and forces sdo to high impedance. when the conversion is complete, the ad7988 - x enters the acquisition phase a nd powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using th e sck falling edge allow s a faster reading rate , provided that it has an acceptable hold time. after the 16th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. ad7988-1/ ad7988-5 sdo data in digital host convert clk vio cnv sck sdi 10231-035 figure 34 . 3 - wire cs mode connection diagram t conv t cyc cnv acquisition acquisition t acq t sck t sckl conversion sck sdo d15 d14 d13 d1 d0 t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh t cnvh sdi = 1 10231-036 figure 35 . 3 - wire cs mode serial interface timing ( sdi high)
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 19 of 24 cs mode 4 - wire this mode is typically used when multiple ad7988 - x device s are connected to an spi - compatible digital host. a connection diagram example using two ad7988 - x device s is shown in figure 36, and the cor responding timing is given in figure 37. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conve rsion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi c an be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conve rsion time elapses and then held high for the maximum conversion time . when the conversion is complete, the ad7988 - x enters the acquisi tion phase and powers down. each adc result can be read by bringing its sdi input low , which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the s ck falling edge allow s a faster reading rate , provided that it has an acceptable hold time. after the 16th sck falling edge or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7988 - x can be read. digital host convert clk data in ad7988-1/ ad7988-5 sdo cnv sck ad7988-1/ ad7988-5 sdo cnv sck cs1 cs2 sdi sdi 10231-037 figure 36 . 4 - wire cs mode connection diagram t conv t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sck cnv t ssdicnv t hsdicnv sdo d15 d13 d14 d1 d0 d15 d14 d1 d0 t hsdo t en 1 2 3 14 15 16 17 18 30 31 32 t dsdo t dis sdi (cs1) sdi (cs2) 10231-038 figure 37 . 4 - wire cs mode serial interface timing
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 20 of 24 chain mode this mode can be use d to da isy - chain multiple ad7988 - x device s on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for s ystems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7988 - x device s is shown in figure 38, and t he corresponding timing is given in figure 39. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a con version and selects the chain mode . in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7988 - x enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read ba ck the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate and, consequently , more ad7988 - x device s in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. digital host convert clk data in ad7988-1/ ad7988-5 sdo cnv a sck ad7988-1/ ad7988-5 sdo cnv b sck 10231-039 sdi sdi figure 38 . chain mode connection diagram t conv t cyc t ssdisck t sckl t sck t hsdisck t acq acquisition t ssckcnv acquisition t sckh conversion t hsckcnv sck cnv sdo b t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d b 1 d b 0 d a 15 d a 14 d a 0 d a 1 d a 1 d a 0 t hsdo 1 2 3 15 16 17 14 18 30 31 32 t dsdo 10231-040 sdi a = 0 sdo a = sdi b figure 39 . chain mode serial interface timing
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 21 of 24 application s information interfacing to black fin ? dsp the ad7988 - x can easily connect to a dsp spi or sport. the spi configuration is straightforward , using the standard spi interface as shown in figure 40 . ad7988-1/ ad7988-5 sck sdo cnv spi_clk spi_miso spi_mosi 10231-041 blackfin d s p figure 40 . typical connection to blackfin spi interface similarly, t he s port interface can be used to interfac e to this adc. the sport interface has some benefits in that it can use direct memory access ( dma ) and provides a lower jitter cnv signal generated from a hardware counter. some glue logic may be required between sport and the ad7988 - x interfac e . the evaluation board for the ad7988 - x interfaces direct ly to the sport of the blackfin - based (adsp - bf - 527) sdp board. the configuration used for t he sport interface requires the addition of some glue logic a s shown in figure 41. the sck input to the adc was gated off when cnv was high to keep the sck line static while converting the data, thereby ensuring the best integrity of the result. this approach uses an and gate and a not gate for the sck path. the other logic gates used on the rsclk and rfs paths are for delay matching purposes and may not be necessary where path lengths are short. this is one approach to using the sport interface for this adc ; there may be other solutions eq ual to this approach. sck sdo cnv tsclk dr tfs rfs rsclk vdrive ad7988-1/ ad7988-5 10231-045 blackfin d s p figure 41 . evaluation board connection to blackfin sport interface layout design t he printed circuit board (pcb) that houses the ad7988 - x so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7988 - x , with all the analog signals on the left side and all the digital signals on the right side, eases this tas k. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7988 - x is used as a shield. fast switching signals, such as cnv or clocks, should neve r run near analog signal paths. avoid c rossover of digital and analog signals . using a t least one ground plane is recommended . it c an be common or split between the digital and analog section. in the latter case, join the planes underneath the ad7988 - x device s. the ad7988 - x voltage reference input , ref , has a dynamic input impedance . decouple ref with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to, but ideally right up against, the ref and gnd pins and connect - ing them with wide, low impedance traces. finally, decouple the power supplies of the ad7988 - x , vdd and vio, with ceram ic capacitors, typically 100 nf, placed close to the ad7988 - x and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 42 and figure 43. evaluating the perfo rmance of the ad7988 - x the evaluation board package for the ad7988 - x ( e va l - ad7988 - 5sdz ) includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb1z . ad7988-1/ ad7988-5 10231-043 figure 42 . example layout of the ad7988 - x (top layer) 10231-044 figure 43 . example layout of the ad7988 - x (bottom layer)
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 22 of 24 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 44 .10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 t op view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-27-2012-b figure 45 . 10- lead lead frame chip scale pac kage [ qfn ( lfcsp _wd) ] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters
data sheet ad7988 - 1/ad7988 - 5 rev. b | page 23 of 24 ordering guide model 1 notes integral nonlinearity temperature range ordering quantity package description package option branding ad7988 - 1brmz 1.25 lsb max ? 40c to +125c tube, 50 10- lead msop rm - 10 c7e ad7988 - 1brmz - rl7 1.25 lsb max ? 40c to +125c reel, 1,000 10- lead msop rm - 10 c7e ad7988 - 1b cp z - rl 1.25 lsb max ? 40c to +125c reel, 5 ,000 10- lead qfn (lfcsp_wd) cp - 10- 9 c7x ad7988 - 1b cp z - rl7 1.25 lsb max ? 40c to +125c reel, 1,5 00 10- lead qfn (lfcsp_wd) cp - 10- 9 c7x ad7988 - 5brmz 1.25 lsb max ? 40c to +125c tube, 50 10- lead msop rm - 10 c7q ad7988 - 5brmz - rl7 1.25 lsb max ? 40c to +125c reel, 1,000 10- lead msop rm - 10 c7q ad7988 - 5 b cp z - rl 1.25 lsb max ? 40c to +125c reel, 5 ,000 10- lead qfn (lfcsp_wd) cp - 10- 9 c7y ad7988 - 5 b cp z - rl7 1.25 lsb max ? 40c to +125c reel, 1, 5 00 10- lead qfn (lfcsp_wd) cp - 10- 9 c7 y eval - ad7988 - 5sdz 2 evaluation board with ad7988 - 5 populated ; use for evaluation of both a d7988 - 1 and ad7988 - 5. eval - sdp - cb1z 3 system demonstration board , used as a controller board for data transfer via usb interface to pc . 1 z = rohs compliant part. 2 this board can be used as a sta ndalone evaluation board or in conjunction with the eval - sdz - cb1z for evaluation/demonstration purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the sd designator.
ad7988 - 1/ad7988 - 5 data sheet rev. b | page 24 of 24 notes ? 2012 analog devices, inc. all rights reserved. trademarks and regi stered trademarks are the property of their respective owners. d10231 - 0- 5/12(b)

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